// Cell names have been changed in this file by netl_namemap on Mon Jan  3 04:00:13 UTC 2022
//////////////////////////////////////////////////////////////////////////////
//
//  pcs_raw_lane.v
//
//  Raw PCS lane control module
//
//  Original Author: Ameer Youssef
//  Current Owner:   Gaurav Dubey
//
//////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015 Synopsys, Inc.  All rights reserved.
//
// SYNOPSYS CONFIDENTIAL - This is an unpublished, proprietary work of
// Synopsys, Inc., and is fully protected under copyright and trade secret
// laws.  You may not view, use, disclose, copy, or distribute this file or
// any information contained herein except pursuant to a valid written
// license agreement. It may not be used, reproduced, or disclosed to others
// except in accordance with the terms and conditions of that agreement.
//
//////////////////////////////////////////////////////////////////////////////
//
//    Perforce Information
//    $Author: gdube $
//    $File: //dwh/up16/main/dev/pcs_raw/dig/rtl/pcs_raw_lane.v $
//    $DateTime: 2019/09/28 22:05:13 $
//    $Revision: #100 $
//
//////////////////////////////////////////////////////////////////////////////

`include "dwc_e12mp_phy_x4_ns_pcs_raw_macros.v"
`include "dwc_e12mp_phy_x4_ns_cr_macros.v"

`timescale 1ns/10fs
module dwc_e12mp_phy_x4_ns_pcs_raw_lane (
// -----------------------------------------------
// PCS INTERFACE
// -----------------------------------------------
input  wire                       cr_clk,
input  wire                       cr_lane_rst,
input  wire [2:0]                 ref_range,

input  wire                       scan_mode,
input  wire                       scan_shift,
input  wire                       scan_shift_cg,
input  wire                       scan_set_rst,

// Common interface
input  wire                       mplla_init_cal_disable,
input  wire                       mpllb_init_cal_disable,
`ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
input  wire                       sram_bypass,
`endif

// Lane_fsm reset signal
input  wire                       fw_rdy,

// Lane interface
input  wire                       lane_tx2rx_ser_lb_en,
input  wire                       lane_rx2tx_par_lb_en,

// TX interface
input  wire                       tx_clk,
input  wire                       tx_clk_rdy,
input  wire [19:0]                tx_data,
input  wire                       tx_data_en,
input  wire                       tx_invert,
input  wire                       tx_reset,
input  wire                       tx_req,
input  wire [1:0]                 tx_pstate,
input  wire                       tx_lpd,
input  wire [1:0]                 tx_width,
input  wire [2:0]                 tx_rate,
input  wire                       tx_mpllb_sel,
input  wire                       tx_mpll_en,
input  wire                       tx_master_mplla_state,
input  wire                       tx_master_mpllb_state,
input  wire                       tx_vboost_en,
input  wire [3:0]                 tx_iboost_lvl,
input  wire                       tx_detrx_req,
output wire                       tx_ack,
output wire                       tx_detrx_result,

// RX interface
input  wire                       rx_reset,
input  wire                       rx_req,
input  wire [1:0]                 rx_rate,
input  wire [1:0]                 rx_width,
input  wire [1:0]                 rx_pstate,
input  wire                       rx_lpd,
input  wire [5:0]                 rx_ref_ld_val,
input  wire [12:0]                rx_vco_ld_val,
input  wire                       rx_cdr_vco_lowfreq,
input  wire                       rx_adapt_afe_en,
input  wire                       rx_adapt_dfe_en,
input  wire [2:0]                 rx_eq_att_lvl,
input  wire [3:0]                 rx_eq_vga1_gain,
input  wire [3:0]                 rx_eq_vga2_gain,
input  wire [2:0]                 rx_eq_ctle_pole,
input  wire [4:0]                 rx_eq_ctle_boost,
input  wire [7:0]                 rx_eq_dfe_tap1,
input  wire                       rx_adapt_req,
input  wire                       rx_adapt_cont,
input  wire                       rx_offcan_cont,
input  wire                       rx_disable_i, // Mantis 6866 - from AON domain
input  wire                       rx_data_en,
input  wire                       rx_cdr_track_en,
input  wire [2:0]                 rx_los_threshold,
`ifdef DWC_E12MP_X4NS_RX_CDR_PPM_DETECTOR_ADDED
input  wire [4:0]                 rx_cdr_ppm_max,
`endif
output wire                       rx_clk,
output wire                       rx_ack,
output wire                       rx_adapt_ack,
output wire [7:0]                 rx_adapt_fom,
output wire [1:0]                 rx_txmain_dir,
output wire [1:0]                 rx_txpre_dir,
output wire [1:0]                 rx_txpost_dir,
output wire                       rx_los,
output wire                       rx_valid,
output wire                       rx_reset_ate,
`ifdef DWC_E12MP_X4NS_RX_CDR_PPM_DETECTOR_ADDED
output wire [5:0]                 rx_ppm_drift,
output wire                       rx_ppm_drift_vld,
`endif

// -----------------------------------------------
// PMA INTERFACE
// -----------------------------------------------

// PMA SUP interface
input  wire                       mplla_en, // un-flopped version from pcs_raw_cmn (Mantis 5662)
input  wire                       mpllb_en, // un-flopped version from pcs_raw_cmn (Mantis 5662)
input  wire                       mplla_state,
input  wire                       mpllb_state,
input  wire                       rtune_ack,

// PMA MPLLA clocks
input  wire                       mplla_word_clk,
input  wire                       mplla_dword_clk,
input  wire                       mplla_qword_clk,
input  wire                       mplla_oword_clk,
input  wire                       mplla_div66_clk,
input  wire                       mplla_div33_clk,
input  wire                       mplla_div16p5_clk,
input  wire                       mplla_div_clk,

// PMA MPLLB clocks
input  wire                       mpllb_word_clk,
input  wire                       mpllb_dword_clk,
input  wire                       mpllb_qword_clk,
input  wire                       mpllb_oword_clk,
input  wire                       mpllb_div_clk,

// PMA Lane interface
output wire                       lane_pma_tx2rx_ser_lb_en,
output wire                       lane_pma_rx2tx_par_lb_en,

// PMA TX interface
output wire                       tx_pma_clk,
output wire                       tx_pma_clk_rdy,
output wire [19:0]                tx_pma_data,
output wire                       tx_pma_data_en,
output wire                       tx_pma_invert,
output wire                       tx_pma_reset,
output wire                       tx_pma_req,
output wire [1:0]                 tx_pma_pstate,
output wire                       tx_pma_lpd,
output wire [1:0]                 tx_pma_width,
output wire [2:0]                 tx_pma_rate,
output wire                       tx_pma_mpllb_sel,
output wire                       tx_pma_vboost_en,
output wire [3:0]                 tx_pma_iboost_lvl,
output wire                       tx_pma_detrx_req,
input  wire                       tx_pma_ack,
input  wire                       tx_pma_detrx_result,

// PMA RX interface
input  wire                       rx_pma_clk,
output wire                       rx_pma_reset,
output wire                       rx_pma_req,
output wire [1:0]                 rx_pma_rate,
output wire [1:0]                 rx_pma_width,
output wire [1:0]                 rx_pma_pstate,
output wire                       rx_pma_lpd,
output wire [5:0]                 rx_pma_ref_ld_val,
output wire [12:0]                rx_pma_vco_ld_val,
output wire                       rx_pma_cdr_vco_lowfreq,
output wire                       rx_pma_adapt_afe_en,
output wire                       rx_pma_adapt_dfe_en,
output wire [2:0]                 rx_pma_eq_att_lvl,
output wire [3:0]                 rx_pma_eq_vga1_gain,
output wire [3:0]                 rx_pma_eq_vga2_gain,
output wire [2:0]                 rx_pma_eq_ctle_pole,
output wire [4:0]                 rx_pma_eq_ctle_boost,
output wire [7:0]                 rx_pma_eq_dfe_tap1,
`ifdef DWC_E12MP_X4NS_PMA_TAP25_INPUT 
output wire [6:0]                 rx_pma_eq_dfe_tap2,
output wire [6:0]                 rx_pma_eq_dfe_tap3,
output wire [6:0]                 rx_pma_eq_dfe_tap4,
output wire [6:0]                 rx_pma_eq_dfe_tap5,
`endif
output wire                       rx_pma_data_en,
output wire                       rx_pma_cdr_track_en,
output wire [2:0]                 rx_pma_los_threshold,
input  wire                       rx_pma_ack,
input  wire [1:0]                 rx_pma_adapt_sts,
input  wire                       rx_pma_los,
input  wire                       rx_pma_valid,

// ----------------------------------------------------
// Internal from/to other Raw PCS lanes (pcs_raw_lane)
// ----------------------------------------------------
input  wire                       lane_mplla_en_in,
input  wire                       lane_mpllb_en_in,
input  wire                       lane_rtune_req_in,
output wire                       lane_mplla_en_out,
output wire                       lane_mpllb_en_out,
output wire                       lane_rtune_req_out,

input  wire                       lanes_cmncal_init,
input  wire                       lanes_cmncal_done,

// -----------------------------------------------
// Internal to/from pcs_raw_aon_lane
// -----------------------------------------------
output wire [31:0]                cr_lane_aon_sel,
output wire [31:0]                cr_lane_aon_sel2,
input  wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr_lane_aon_rd_data,

// Fast flags (from aon_lane register)
input  wire                       rx_fast_vco_cal_r,
input  wire                       rx_fast_vco_wait_r,
input  wire                       rx_fast_pwrup_r,
input  wire                       tx_fast_rxdet_r,
input  wire                       tx_fast_cmn_mode_r,
input  wire                       tx_fast_sup_r,
input  wire                       rx_fast_dfe_adapt_r,
input  wire                       rx_fast_afe_adapt_r,
input  wire                       rx_fast_iq_cal_r,
input  wire                       rx_fast_reflvl_cal_r,
input  wire                       rx_fast_bypass_cal_r,
input  wire                       rx_fast_dfe_cal_r,
input  wire                       rx_fast_afe_cal_r,
input  wire                       rx_fast_adapt_r,
input  wire                       rx_fast_startup_cal_r,

input  wire [6:0]                 rx_fast_flags_rsvd_r,
input  wire                       rx_fast_cont_afe_cal_r,
input  wire                       rx_fast_cont_phase_cal_r,
input  wire                       rx_fast_cont_data_cal_r,
input  wire                       rx_fast_cont_adapt_r,
input  wire                       rx_fast_cont_cal_adapt_r,

// Initial power-up done status (from aon_lane register)
input                             lane_init_pwrup_done_r,

// RX Adaptation Status and Values (from aon_lane registers)
input  wire [7:0]                 rx_att_adpt_val_r,
input  wire [9:0]                 rx_vga_adpt_val_r,
input  wire [2:0]                 rx_ctle_pole_adpt_val_r,
input  wire [9:0]                 rx_ctle_boost_adpt_val_r,
input  wire [12:0]                rx_dfe_tap1_adpt_val_r,
input  wire [11:0]                rx_dfe_tap2_adpt_val_r,
input  wire [11:0]                rx_dfe_tap3_adpt_val_r,
input  wire [11:0]                rx_dfe_tap4_adpt_val_r,
input  wire [11:0]                rx_dfe_tap5_adpt_val_r,
input  wire                       rx_adpt_done_r,

`ifdef DWC_E12MP_X4NS_RX_CDR_PPM_DETECTOR_ADDED
input wire [11:0]                 rx_cdr_recovery_time_r,
input wire                        rx_cdr_detector_en_r,
input wire                        rx_cdr_ppm_monitor_mode_r,
input wire                        rx_cdr_detector_dis_in_adapt_r,
`endif

// -----------------------------------------------
// Internal to/from pcs_raw_cmn
// -----------------------------------------------
// CREG interface input (used for registers in pcs_raw_lane logic)
input  wire [3:0]                 cr_chan_addr,
input  wire [`DWC_E12MP_X4NS_CR_ADDR_RANGE] cr_addr,
input  wire                       cr_wr_en,
input  wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr_wr_data,
input  wire                       cr_rd_en,
output wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr_rd_data,

// CREG interface output to Memory-Aribter
input  wire                       cr_mem_ack,
input  wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr_mem_rd_data,
output wire                       cr_mem_req,
output wire [`DWC_E12MP_X4NS_CR_ADDR_RANGE] cr_mem_addr,
output wire                       cr_mem_wr_en,
output wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr_mem_wr_data,
output wire                       cr_mem_rd_en,

// CREG interface output to Register-Aribter
input  wire                       cr_reg_ack,
input  wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr_reg_rd_data,
output wire                       cr_reg_req,
output wire [`DWC_E12MP_X4NS_CR_ADDR_RANGE] cr_reg_addr,
output wire                       cr_reg_wr_en,
output wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr_reg_wr_data,
output wire                       cr_reg_rd_en
);

wire         mplla_init_cal_disable_i;
wire         mpllb_init_cal_disable_i;
wire         lane_tx2rx_ser_lb_en_i;
wire         lane_rx2tx_par_lb_en_i;
wire         tx_clk_i;
wire         tx_clk_rdy_i;
wire [19:0]  tx_data_i;
wire         tx_data_en_i;
wire         tx_invert_i;
wire         tx_reset_i;
wire         tx_req_i;
wire [1:0]   tx_pstate_i;
wire         tx_lpd_i;
wire [1:0]   tx_width_i;
wire [2:0]   tx_rate_i;
wire         tx_mpllb_sel_i;
wire         tx_mpll_en_i;
wire         tx_master_mplla_state_i;
wire         tx_master_mpllb_state_i;
wire         tx_vboost_en_i;
wire [3:0]   tx_iboost_lvl_i;
wire         tx_detrx_req_i;
wire         tx_ack_i;
wire         tx_detrx_result_i;
wire         rx_reset_i;
wire         rx_req_i;
wire [1:0]   rx_rate_i;
wire [1:0]   rx_width_i;
wire [1:0]   rx_pstate_i;
wire         rx_lpd_i;
wire [5:0]   rx_ref_ld_val_i;
wire [12:0]  rx_vco_ld_val_i;
wire         rx_cdr_vco_lowfreq_i;
wire         rx_adapt_afe_en_i;
wire         rx_adapt_dfe_en_i;
wire [2:0]   rx_eq_att_lvl_i;
wire [3:0]   rx_eq_vga1_gain_i;
wire [3:0]   rx_eq_vga2_gain_i;
wire [2:0]   rx_eq_ctle_pole_i;
wire [4:0]   rx_eq_ctle_boost_i;
wire [7:0]   rx_eq_dfe_tap1_i;
wire         rx_data_en_i;
wire         rx_cdr_track_en_i;
wire [2:0]   rx_los_threshold_i;
wire         rx_adapt_req_i;
`ifdef DWC_E12MP_X4NS_RX_CDR_PPM_DETECTOR_ADDED
wire         rx_adapt_req_sync;
`endif
wire         rx_adapt_cont_i;
wire         rx_offcan_cont_i;
wire         rx_ack_i;
wire         rx_los_i;
wire         rx_valid_i;
`ifdef DWC_E12MP_X4NS_RX_CDR_PPM_DETECTOR_ADDED
wire [4:0]   rx_cdr_ppm_max_i;
`endif
wire [1:0]   rx_adapt_sts_i;
wire         scan_mode_i;
wire         scan_shift_cg_i;
wire         scan_set_rst_i;
wire         lane_mplla_en_in_i;
wire         lane_mpllb_en_in_i;
wire         lane_mplla_en_out_i;
wire         lane_mpllb_en_out_i;
wire         mplla_en_i;
wire         mpllb_en_i;
wire         mplla_state_i;
wire         mpllb_state_i;
wire         mplla_word_clk_i;
wire         mplla_dword_clk_i;
wire         mplla_qword_clk_i;
wire         mplla_oword_clk_i;
wire         mplla_div66_clk_i;
wire         mplla_div33_clk_i;
wire         mplla_div16p5_clk_i;
wire         mplla_div_clk_i;
wire         mpllb_word_clk_i;
wire         mpllb_dword_clk_i;
wire         mpllb_qword_clk_i;
wire         mpllb_oword_clk_i;
wire         mpllb_div_clk_i;
wire         rx_clk_i;
wire         lane_pma_tx2rx_ser_lb_en_i;
wire         lane_pma_rx2tx_par_lb_en_i;
wire         tx_pma_clk_i;
wire         tx_pma_clk_rdy_i;
wire [19:0]  tx_pma_data_i;
wire         tx_pma_data_en_i;
wire         tx_pma_invert_i;
wire         tx_pma_reset_i;
wire         tx_pma_req_i;
wire [1:0]   tx_pma_pstate_i;
wire         tx_pma_lpd_i;
wire [1:0]   tx_pma_width_i;
wire [2:0]   tx_pma_rate_i;
wire         tx_pma_mpllb_sel_i;
wire         tx_pma_vboost_en_i;
wire [3:0]   tx_pma_iboost_lvl_i;
wire         tx_pma_detrx_req_i;
wire         tx_pma_ack_i;
wire         tx_pma_detrx_result_i;
wire         rx_pma_reset_i;
wire         rx_pma_req_i;
wire [1:0]   rx_pma_rate_i;
wire [1:0]   rx_pma_width_i;
wire [1:0]   rx_pma_pstate_i;
wire         rx_pma_lpd_i;
wire [5:0]   rx_pma_ref_ld_val_i;
wire [12:0]  rx_pma_vco_ld_val_i;
wire         rx_pma_cdr_vco_lowfreq_i;
wire         rx_pma_adapt_afe_en_i;
wire         rx_pma_adapt_dfe_en_i;
wire [2:0]   rx_pma_eq_att_lvl_i;
wire [3:0]   rx_pma_eq_vga1_gain_i;
wire [3:0]   rx_pma_eq_vga2_gain_i;
wire [2:0]   rx_pma_eq_ctle_pole_i;
wire [4:0]   rx_pma_eq_ctle_boost_i;
wire [7:0]   rx_pma_eq_dfe_tap1_i;
wire [6:0]   rx_pma_eq_dfe_tap2_i;
wire [6:0]   rx_pma_eq_dfe_tap3_i;
wire [6:0]   rx_pma_eq_dfe_tap4_i;
wire [6:0]   rx_pma_eq_dfe_tap5_i;
wire         rx_pma_data_en_i;
wire         rx_pma_cdr_track_en_i;
wire [2:0]   rx_pma_los_threshold_i;
wire         rx_pma_ack_i;
wire [1:0]   rx_pma_adapt_sts_i;
wire         rx_pma_los_i;
wire         rx_pma_valid_i;

wire         irq;
wire         irq_msk_clr;

wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr_lane_pcs_xface_rd_data;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr_lane_fsm_rd_data;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr_irq_ctl_rd_data;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr_lane_pma_xface_rd_data;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr_tx_ctl_rd_data;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr_rx_ctl_rd_data;
`ifdef DWC_E12MP_X4NS_RX_CDR_PPM_DETECTOR_ADDED
wire [24:0]                cr_lane_pcs_xface_sel;
`else
wire [23:0]                cr_lane_pcs_xface_sel;
`endif
wire [31:0]                cr_lane_fsm_sel;
wire [13:0]                cr_irq_ctl_sel;
wire [8:0]                 cr_lane_pma_xface_sel;
wire [1:0]                 cr_tx_ctl_sel;
`ifdef DWC_E12MP_X4NS_RX_CDR_PPM_DETECTOR_ADDED
wire [6:0]                 cr_rx_ctl_sel;
`else
wire [4:0]                 cr_rx_ctl_sel;
`endif

// PCS Interface override

// %%CREG_BLOCK PCS_XF - pcs_raw_lane_pcs_xface(0x00)
//
dwc_e12mp_phy_x4_ns_pcs_raw_lane_pcs_xface lane_pcs_xface 
  (
  // PCS side
  .mplla_init_cal_disable    (mplla_init_cal_disable),
  .mpllb_init_cal_disable    (mpllb_init_cal_disable),
  .lane_tx2rx_ser_lb_en      (lane_tx2rx_ser_lb_en),
  .lane_rx2tx_par_lb_en      (lane_rx2tx_par_lb_en),
  .tx_clk                    (tx_clk),
  .tx_clk_rdy                (tx_clk_rdy),
  .tx_data                   (tx_data),
  .tx_data_en                (tx_data_en),
  .tx_invert                 (tx_invert),
  .tx_reset                  (tx_reset),
  .tx_req                    (tx_req),
  .tx_pstate                 (tx_pstate),
  .tx_lpd                    (tx_lpd),
  .tx_width                  (tx_width),
  .tx_rate                   (tx_rate),
  .tx_mpllb_sel              (tx_mpllb_sel),
  .tx_mpll_en                (tx_mpll_en),
  .tx_master_mplla_state     (tx_master_mplla_state),
  .tx_master_mpllb_state     (tx_master_mpllb_state),
  .tx_vboost_en              (tx_vboost_en),
  .tx_iboost_lvl             (tx_iboost_lvl),
  .tx_detrx_req              (tx_detrx_req),
  .tx_ack                    (tx_ack),
  .tx_detrx_result           (tx_detrx_result),
  .rx_reset                  (rx_reset),
  .rx_req                    (rx_req),
  .rx_rate                   (rx_rate),
  .rx_width                  (rx_width),
  .rx_pstate                 (rx_pstate),
  .rx_lpd                    (rx_lpd),
  .rx_ref_ld_val             (rx_ref_ld_val),
  .rx_vco_ld_val             (rx_vco_ld_val),
  .rx_cdr_vco_lowfreq        (rx_cdr_vco_lowfreq),
  .rx_adapt_afe_en           (rx_adapt_afe_en),
  .rx_adapt_dfe_en           (rx_adapt_dfe_en),
  .rx_eq_att_lvl             (rx_eq_att_lvl),
  .rx_eq_vga1_gain           (rx_eq_vga1_gain),
  .rx_eq_vga2_gain           (rx_eq_vga2_gain),
  .rx_eq_ctle_pole           (rx_eq_ctle_pole),
  .rx_eq_ctle_boost          (rx_eq_ctle_boost),
  .rx_eq_dfe_tap1            (rx_eq_dfe_tap1),
  .rx_adapt_req              (rx_adapt_req),
  .rx_adapt_cont             (rx_adapt_cont),
  .rx_offcan_cont            (rx_offcan_cont),
  .rx_data_en                (rx_data_en),
  .rx_cdr_track_en           (rx_cdr_track_en),
  .rx_los_threshold          (rx_los_threshold),
  .rx_clk                    (rx_clk),
  .rx_ack                    (rx_ack),
  .rx_los                    (rx_los),
  .rx_valid                  (rx_valid),
  .rx_adapt_ack              (rx_adapt_ack),
  .rx_adapt_fom              (rx_adapt_fom),
  .rx_txmain_dir             (rx_txmain_dir),
  .rx_txpre_dir              (rx_txpre_dir),
  .rx_txpost_dir             (rx_txpost_dir),
`ifdef DWC_E12MP_X4NS_RX_CDR_PPM_DETECTOR_ADDED
  .rx_cdr_ppm_max            (rx_cdr_ppm_max),
`endif
  .scan_mode                 (scan_mode),
  .scan_shift_cg             (scan_shift_cg),
  .scan_set_rst              (scan_set_rst),
  .cr_chan_addr              (cr_chan_addr),

  // PHY side
  .mplla_init_cal_disable_i  (mplla_init_cal_disable_i),
  .mpllb_init_cal_disable_i  (mpllb_init_cal_disable_i),
  .lane_tx2rx_ser_lb_en_i    (lane_tx2rx_ser_lb_en_i),
  .lane_rx2tx_par_lb_en_i    (lane_rx2tx_par_lb_en_i),
  .tx_clk_i                  (tx_clk_i),
  .tx_clk_rdy_i              (tx_clk_rdy_i),
  .tx_data_i                 (tx_data_i),
  .tx_data_en_i              (tx_data_en_i),
  .tx_invert_i               (tx_invert_i),
  .tx_reset_i                (tx_reset_i),
  .tx_req_i                  (tx_req_i),
  .tx_pstate_i               (tx_pstate_i),
  .tx_lpd_i                  (tx_lpd_i),
  .tx_rate_i                 (tx_rate_i),
  .tx_width_i                (tx_width_i),
  .tx_mpllb_sel_i            (tx_mpllb_sel_i),
  .tx_mpll_en_i              (tx_mpll_en_i),
  .tx_master_mplla_state_i   (tx_master_mplla_state_i),
  .tx_master_mpllb_state_i   (tx_master_mpllb_state_i),
  .tx_vboost_en_i            (tx_vboost_en_i),
  .tx_iboost_lvl_i           (tx_iboost_lvl_i),
  .tx_detrx_req_i            (tx_detrx_req_i),
  .tx_ack_i                  (tx_ack_i),
  .tx_detrx_result_i         (tx_detrx_result_i),
  .rx_reset_ate              (rx_reset_ate),
  .rx_reset_i                (rx_reset_i),
  .rx_req_i                  (rx_req_i),
  .rx_rate_i                 (rx_rate_i),
  .rx_width_i                (rx_width_i),
  .rx_pstate_i               (rx_pstate_i),
  .rx_lpd_i                  (rx_lpd_i),
  .rx_ref_ld_val_i           (rx_ref_ld_val_i),
  .rx_vco_ld_val_i           (rx_vco_ld_val_i),
  .rx_cdr_vco_lowfreq_i      (rx_cdr_vco_lowfreq_i),
  .rx_adapt_afe_en_i         (rx_adapt_afe_en_i),
  .rx_adapt_dfe_en_i         (rx_adapt_dfe_en_i),
  .rx_eq_att_lvl_i           (rx_eq_att_lvl_i),
  .rx_eq_vga1_gain_i         (rx_eq_vga1_gain_i),
  .rx_eq_vga2_gain_i         (rx_eq_vga2_gain_i),
  .rx_eq_ctle_pole_i         (rx_eq_ctle_pole_i),
  .rx_eq_ctle_boost_i        (rx_eq_ctle_boost_i),
  .rx_eq_dfe_tap1_i          (rx_eq_dfe_tap1_i),
  .rx_adapt_req_i            (rx_adapt_req_i),
  .rx_adapt_cont_i           (rx_adapt_cont_i),
  .rx_offcan_cont_i          (rx_offcan_cont_i),
  .rx_data_en_i              (rx_data_en_i),
  .rx_cdr_track_en_i         (rx_cdr_track_en_i),
  .rx_los_threshold_i        (rx_los_threshold_i),
  .rx_clk_i                  (rx_clk_i),
  .rx_ack_i                  (rx_ack_i),
  .rx_los_i                  (rx_los_i),
  .rx_valid_i                (rx_valid_i),
`ifdef DWC_E12MP_X4NS_RX_CDR_PPM_DETECTOR_ADDED
  .rx_cdr_ppm_max_i          (rx_cdr_ppm_max_i),
`endif
  .scan_mode_i               (scan_mode_i),
  .scan_shift_cg_i           (scan_shift_cg_i),
  .scan_set_rst_i            (scan_set_rst_i),

  // CREG Interface
  .cr_clk                    (cr_clk),
  .cr_rst                    (cr_lane_rst),
  .cr_wr_en                  (cr_wr_en),
  .cr_wr_data                (cr_wr_data),
  .cr_rd_data                (cr_lane_pcs_xface_rd_data),
  .cr_sel                    (cr_lane_pcs_xface_sel)
);

// to prevent C26 DFT violations and cover the OR-gate in scan, 
// block cr_lane_rst in scan mode, 
// which already has the scan reset on it. 
wire cr_lane_rst_w_scan;
dwc_e12mp_phy_x4_ns_gen_clk_and2 cr_lane_rst_scan_and (
  .out (cr_lane_rst_w_scan), 
  .clk (cr_lane_rst), 
  .en  (~scan_mode_i)
);

// Generate the lane_fw_rst signal for the lane_fsm
// Mantis 7191 - Use separate resets for control registers
// inside the lane_fsm
wire fsm_rst_async = ~fw_rdy | cr_lane_rst_w_scan;
wire fsm_rst;

// Synchronize to cr_clk
dwc_e12mp_phy_x4_ns_gen_rst_sync lane_fsm_rst_sync (
  .sync_rst       (fsm_rst),
  .clk            (cr_clk),
  .async_rst      (fsm_rst_async),
  .scan_mode_i    (scan_mode_i),
  .scan_set_rst_i (scan_set_rst_i)
);

// %%CREG_BLOCK FSM - pcs_raw_lane_fsm(0x20)
//
dwc_e12mp_phy_x4_ns_pcs_raw_lane_fsm fsm (
   // Clocks and resets
  .cr_clk                   (cr_clk),
  .cr_rst                   (cr_lane_rst),
  .fsm_rst                  (fsm_rst),
  // Interrupt request
  .irq                      (irq),
  // Interrupt mask clear   
  .irq_msk_clr              (irq_msk_clr),
  // Control/status signals
  .rx_adapt_sts_i           (rx_adapt_sts_i),
  .cr_chan_addr             (cr_chan_addr),
`ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
// Pass in SRAM control if supported
  .sram_bypass              (sram_bypass),
`endif
  // Fast flags (from aon_lane register)
  .rx_fast_vco_cal_r        (rx_fast_vco_cal_r),
  .rx_fast_vco_wait_r       (rx_fast_vco_wait_r),
  .rx_fast_pwrup_r          (rx_fast_pwrup_r),
  .tx_fast_rxdet_r          (tx_fast_rxdet_r),
  .tx_fast_cmn_mode_r       (tx_fast_cmn_mode_r),
  .tx_fast_sup_r            (tx_fast_sup_r),
  .rx_fast_dfe_adapt_r      (rx_fast_dfe_adapt_r),
  .rx_fast_afe_adapt_r      (rx_fast_afe_adapt_r),
  .rx_fast_iq_cal_r         (rx_fast_iq_cal_r),
  .rx_fast_reflvl_cal_r     (rx_fast_reflvl_cal_r),
  .rx_fast_bypass_cal_r     (rx_fast_bypass_cal_r),
  .rx_fast_dfe_cal_r        (rx_fast_dfe_cal_r),
  .rx_fast_afe_cal_r        (rx_fast_afe_cal_r),
  .rx_fast_adapt_r          (rx_fast_adapt_r),
  .rx_fast_startup_cal_r    (rx_fast_startup_cal_r),
  .rx_fast_flags_rsvd_r     (rx_fast_flags_rsvd_r),
  .rx_fast_cont_afe_cal_r   (rx_fast_cont_afe_cal_r),
  .rx_fast_cont_phase_cal_r (rx_fast_cont_phase_cal_r),
  .rx_fast_cont_data_cal_r  (rx_fast_cont_data_cal_r),
  .rx_fast_cont_adapt_r     (rx_fast_cont_adapt_r),
  .rx_fast_cont_cal_adapt_r (rx_fast_cont_cal_adapt_r),
  .lanes_cmncal_init        (lanes_cmncal_init),
  .lanes_cmncal_done        (lanes_cmncal_done),
  // CREG interface output to Memory-Aribter
  .cr_mem_ack               (cr_mem_ack),
  .cr_mem_rd_data           (cr_mem_rd_data),
  .cr_mem_req               (cr_mem_req),
  .cr_mem_addr              (cr_mem_addr),
  .cr_mem_wr_data           (cr_mem_wr_data),
  .cr_mem_wr_en             (cr_mem_wr_en),
  .cr_mem_rd_en             (cr_mem_rd_en),
  // CREG interface output to Register-Aribter
  .cr_reg_ack               (cr_reg_ack),
  .cr_reg_rd_data           (cr_reg_rd_data),
  .cr_reg_req               (cr_reg_req),
  .cr_reg_addr              (cr_reg_addr),
  .cr_reg_wr_en             (cr_reg_wr_en),
  .cr_reg_wr_data           (cr_reg_wr_data),
  .cr_reg_rd_en             (cr_reg_rd_en),
  // CREG interface (accessing CREGs in the lane fsm block)
  .cr_rd_data               (cr_lane_fsm_rd_data),
  .cr_wr_data               (cr_wr_data),
  .cr_wr_en                 (cr_wr_en),
  .cr_sel                   (cr_lane_fsm_sel),
  // Scan interface
  .scan_mode_i              (scan_mode_i),
  .scan_set_rst_i           (scan_set_rst_i)
);

// %%CREG_BLOCK AON - pcs_raw_aon_lane(0x40)
//
// This block is instantiated under pcs_raw_aon_xN
// but keeping creg block comment here to indicate
// the block's address
//pcs_raw_aon_lane aon_lane (

// %%CREG_BLOCK IRQ_CTL - pcs_raw_irq_ctl(0x80)
//
dwc_e12mp_phy_x4_ns_pcs_raw_irq_ctl irq_ctl (
   // Clocks and resets
  .cr_clk                (cr_clk),
  .cr_rst                (cr_lane_rst),
  // Asynchronous interrupt sources
  .rx_reset_i            (rx_reset_i),
  .rx_req_i              (rx_req_i),
  .rx_rate_i             (rx_rate_i),
  .rx_width_i            (rx_width_i),
  .rx_ref_ld_val_i       (rx_ref_ld_val_i),
  .rx_vco_ld_val_i       (rx_vco_ld_val_i),
  .rx_cdr_vco_lowfreq_i  (rx_cdr_vco_lowfreq_i),
  .rx_pstate_i           (rx_pstate_i),
  .rx_adapt_req_i        (rx_adapt_req_i),

`ifdef  DWC_E12MP_X4NS_RX_CDR_PPM_DETECTOR_ADDED
  // Synchronous interrupt sources
  .rx_adapt_req_sync    (rx_adapt_req_sync),
`endif

  // Interrupt mask clear
  .irq_msk_clr           (irq_msk_clr),
  // Combined interrupt request
  .irq                   (irq),
  // SCAN interface
  .scan_mode_i           (scan_mode_i),
  .scan_set_rst_i        (scan_set_rst_i),
  // CREG interface
  .cr_rd_data            (cr_irq_ctl_rd_data),
  .cr_wr_data            (cr_wr_data),
  .cr_wr_en              (cr_wr_en),
  .cr_sel                (cr_irq_ctl_sel)
);

// %%CREG_BLOCK PMA_XF - pcs_raw_lane_pma_xface(0xA0)
//
dwc_e12mp_phy_x4_ns_pcs_raw_lane_pma_xface lane_pma_xface 
  (
  // PMA side
  .lane_mplla_en_in          (lane_mplla_en_in),
  .lane_mpllb_en_in          (lane_mpllb_en_in),
  .lane_rtune_req_in         (lane_rtune_req_in),
  .lane_mplla_en_out         (lane_mplla_en_out),
  .lane_mpllb_en_out         (lane_mpllb_en_out),
  .lane_rtune_req_out        (lane_rtune_req_out),
  .mplla_en                  (mplla_en),
  .mpllb_en                  (mpllb_en),
  .mplla_state               (mplla_state),
  .mpllb_state               (mpllb_state),
  .rtune_ack                 (rtune_ack),
  .mplla_word_clk            (mplla_word_clk),
  .mplla_dword_clk           (mplla_dword_clk),
  .mplla_qword_clk           (mplla_qword_clk),
  .mplla_oword_clk           (mplla_oword_clk),
  .mplla_div66_clk           (mplla_div66_clk),
  .mplla_div33_clk           (mplla_div33_clk),
  .mplla_div16p5_clk         (mplla_div16p5_clk),
  .mplla_div_clk             (mplla_div_clk),
  .mpllb_word_clk            (mpllb_word_clk),
  .mpllb_dword_clk           (mpllb_dword_clk),
  .mpllb_qword_clk           (mpllb_qword_clk),
  .mpllb_oword_clk           (mpllb_oword_clk),
  .mpllb_div_clk             (mpllb_div_clk),
  .lane_tx2rx_ser_lb_en      (lane_pma_tx2rx_ser_lb_en),
  .lane_rx2tx_par_lb_en      (lane_pma_rx2tx_par_lb_en),
  .tx_clk                    (tx_pma_clk),
  .tx_clk_rdy                (tx_pma_clk_rdy),
  .tx_data                   (tx_pma_data),
  .tx_data_en                (tx_pma_data_en),
  .tx_invert                 (tx_pma_invert),
  .tx_reset                  (tx_pma_reset),
  .tx_req                    (tx_pma_req),
  .tx_pstate                 (tx_pma_pstate),
  .tx_lpd                    (tx_pma_lpd),
  .tx_width                  (tx_pma_width),
  .tx_rate                   (tx_pma_rate),
  .tx_mpllb_sel              (tx_pma_mpllb_sel),
  .tx_vboost_en              (tx_pma_vboost_en),
  .tx_iboost_lvl             (tx_pma_iboost_lvl),
  .tx_detrx_req              (tx_pma_detrx_req),
  .tx_ack                    (tx_pma_ack),
  .tx_detrx_result           (tx_pma_detrx_result),
  .rx_clk                    (rx_pma_clk),
  .rx_reset                  (rx_pma_reset),
  .rx_req                    (rx_pma_req),
  .rx_rate                   (rx_pma_rate),
  .rx_width                  (rx_pma_width),
  .rx_pstate                 (rx_pma_pstate),
  .rx_lpd                    (rx_pma_lpd),
  .rx_ref_ld_val             (rx_pma_ref_ld_val),
  .rx_vco_ld_val             (rx_pma_vco_ld_val),
  .rx_cdr_vco_lowfreq        (rx_pma_cdr_vco_lowfreq),
  .rx_adapt_afe_en           (rx_pma_adapt_afe_en),
  .rx_adapt_dfe_en           (rx_pma_adapt_dfe_en),
  .rx_eq_att_lvl             (rx_pma_eq_att_lvl),
  .rx_eq_vga1_gain           (rx_pma_eq_vga1_gain),
  .rx_eq_vga2_gain           (rx_pma_eq_vga2_gain),
  .rx_eq_ctle_pole           (rx_pma_eq_ctle_pole),
  .rx_eq_ctle_boost          (rx_pma_eq_ctle_boost),
  .rx_eq_dfe_tap1            (rx_pma_eq_dfe_tap1),
  `ifdef DWC_E12MP_X4NS_PMA_TAP25_INPUT 
  .rx_eq_dfe_tap2            (rx_pma_eq_dfe_tap2),
  .rx_eq_dfe_tap3            (rx_pma_eq_dfe_tap3),
  .rx_eq_dfe_tap4            (rx_pma_eq_dfe_tap4),
  .rx_eq_dfe_tap5            (rx_pma_eq_dfe_tap5),
  `else
  .rx_eq_dfe_tap2            (),
  .rx_eq_dfe_tap3            (),
  .rx_eq_dfe_tap4            (),
  .rx_eq_dfe_tap5            (),
  `endif
  .rx_data_en                (rx_pma_data_en),
  .rx_cdr_track_en           (rx_pma_cdr_track_en),
  .rx_los_threshold          (rx_pma_los_threshold),
  .rx_ack                    (rx_pma_ack),
  .rx_adapt_sts              (rx_pma_adapt_sts),
  .rx_los                    (rx_pma_los),
  .rx_valid                  (rx_pma_valid),

  // Raw PCS side
  .lane_mplla_en_in_i        (lane_mplla_en_in_i),
  .lane_mpllb_en_in_i        (lane_mpllb_en_in_i),
  .lane_mplla_en_out_i       (lane_mplla_en_out_i),
  .lane_mpllb_en_out_i       (lane_mpllb_en_out_i),
  .mplla_en_i                (mplla_en_i),
  .mpllb_en_i                (mpllb_en_i),
  .mplla_state_i             (mplla_state_i),
  .mpllb_state_i             (mpllb_state_i),
  .mplla_word_clk_i          (mplla_word_clk_i),
  .mplla_dword_clk_i         (mplla_dword_clk_i),
  .mplla_qword_clk_i         (mplla_qword_clk_i),
  .mplla_oword_clk_i         (mplla_oword_clk_i),
  .mplla_div66_clk_i         (mplla_div66_clk_i),
  .mplla_div33_clk_i         (mplla_div33_clk_i),
  .mplla_div16p5_clk_i       (mplla_div16p5_clk_i),
  .mplla_div_clk_i           (mplla_div_clk_i),
  .mpllb_word_clk_i          (mpllb_word_clk_i),
  .mpllb_dword_clk_i         (mpllb_dword_clk_i),
  .mpllb_qword_clk_i         (mpllb_qword_clk_i),
  .mpllb_oword_clk_i         (mpllb_oword_clk_i),
  .mpllb_div_clk_i           (mpllb_div_clk_i),
  .mplla_init_cal_disable_i  (mplla_init_cal_disable_i),
  .mpllb_init_cal_disable_i  (mpllb_init_cal_disable_i),
  .lane_tx2rx_ser_lb_en_i    (lane_pma_tx2rx_ser_lb_en_i),
  .lane_rx2tx_par_lb_en_i    (lane_pma_rx2tx_par_lb_en_i),
  .tx_clk_i                  (tx_pma_clk_i),
  .tx_clk_rdy_i              (tx_pma_clk_rdy_i),
  .tx_data_i                 (tx_pma_data_i),
  .tx_data_en_i              (tx_pma_data_en_i),
  .tx_invert_i               (tx_pma_invert_i),
  .tx_reset_i                (tx_pma_reset_i),
  .tx_req_i                  (tx_pma_req_i),
  .tx_pstate_i               (tx_pma_pstate_i),
  .tx_lpd_i                  (tx_pma_lpd_i),
  .tx_width_i                (tx_pma_width_i),
  .tx_rate_i                 (tx_pma_rate_i),
  .tx_mpllb_sel_i            (tx_pma_mpllb_sel_i),
  .tx_vboost_en_i            (tx_pma_vboost_en_i),
  .tx_iboost_lvl_i           (tx_pma_iboost_lvl_i),
  .tx_detrx_req_i            (tx_pma_detrx_req_i),
  .tx_ack_i                  (tx_pma_ack_i),
  .tx_detrx_result_i         (tx_pma_detrx_result_i),
  .rx_clk_i                  (rx_clk_i),
  .rx_reset_i                (rx_pma_reset_i),
  .rx_req_i                  (rx_pma_req_i),
  .rx_rate_i                 (rx_pma_rate_i),
  .rx_width_i                (rx_pma_width_i),
  .rx_pstate_i               (rx_pma_pstate_i),
  .rx_lpd_i                  (rx_pma_lpd_i),
  .rx_ref_ld_val_i           (rx_pma_ref_ld_val_i),
  .rx_vco_ld_val_i           (rx_pma_vco_ld_val_i),
  .rx_cdr_vco_lowfreq_i      (rx_pma_cdr_vco_lowfreq_i),
  .rx_adapt_afe_en_i         (rx_pma_adapt_afe_en_i),
  .rx_adapt_dfe_en_i         (rx_pma_adapt_dfe_en_i),
  .rx_eq_att_lvl_i           (rx_pma_eq_att_lvl_i),
  .rx_eq_vga1_gain_i         (rx_pma_eq_vga1_gain_i),
  .rx_eq_vga2_gain_i         (rx_pma_eq_vga2_gain_i),
  .rx_eq_ctle_pole_i         (rx_pma_eq_ctle_pole_i),
  .rx_eq_ctle_boost_i        (rx_pma_eq_ctle_boost_i),
  .rx_eq_dfe_tap1_i          (rx_pma_eq_dfe_tap1_i),
  .rx_eq_dfe_tap2_i          (rx_pma_eq_dfe_tap2_i),
  .rx_eq_dfe_tap3_i          (rx_pma_eq_dfe_tap3_i),
  .rx_eq_dfe_tap4_i          (rx_pma_eq_dfe_tap4_i),
  .rx_eq_dfe_tap5_i          (rx_pma_eq_dfe_tap5_i),
  .rx_data_en_i              (rx_pma_data_en_i),
  .rx_cdr_track_en_i         (rx_pma_cdr_track_en_i),
  .rx_los_threshold_i        (rx_pma_los_threshold_i),
  .rx_ack_i                  (rx_pma_ack_i),
  .rx_adapt_sts_i            (rx_pma_adapt_sts_i),
  .rx_los_i                  (rx_pma_los_i),
  .rx_valid_i                (rx_pma_valid_i),
  // CREG Interface
  .cr_clk                    (cr_clk),
  .cr_rst                    (cr_lane_rst),
  .cr_wr_en                  (cr_wr_en),
  .cr_wr_data                (cr_wr_data),
  .cr_rd_data                (cr_lane_pma_xface_rd_data),
  .cr_sel                    (cr_lane_pma_xface_sel)
);

assign lane_pma_tx2rx_ser_lb_en_i = lane_tx2rx_ser_lb_en_i;
assign lane_pma_rx2tx_par_lb_en_i = lane_rx2tx_par_lb_en_i;
assign tx_pma_clk_rdy_i           = tx_clk_rdy_i;
assign tx_pma_data_i              = tx_data_i;
assign tx_pma_data_en_i           = tx_data_en_i;
assign tx_pma_invert_i            = tx_invert_i;
assign tx_pma_vboost_en_i         = tx_vboost_en_i;
assign tx_pma_iboost_lvl_i        = tx_iboost_lvl_i;
assign rx_adapt_sts_i             = rx_pma_adapt_sts_i;
assign rx_pma_los_threshold_i     = rx_los_threshold_i;

// %%CREG_BLOCK TX_CTL - pcs_raw_tx_ctl(0xC0)
//
dwc_e12mp_phy_x4_ns_pcs_raw_tx_ctl tx_ctl (
  // Clocks and resets
  .cr_clk                  (cr_clk),
  .cr_rst                  (cr_lane_rst),
  .ref_range               (ref_range),
  // PCS TX interface
  .tx_clk_i                (tx_clk_i),
  .tx_reset_i              (tx_reset_i),
  .tx_req_i                (tx_req_i),
  .tx_pstate_i             (tx_pstate_i),
  .tx_lpd_i                (tx_lpd_i),
  .tx_width_i              (tx_width_i),
  .tx_rate_i               (tx_rate_i),
  .tx_mpllb_sel_i          (tx_mpllb_sel_i),
  .tx_mpll_en_i            (tx_mpll_en_i),
  .tx_master_mplla_state_i (tx_master_mplla_state_i),
  .tx_master_mpllb_state_i (tx_master_mpllb_state_i),
  .tx_detrx_req_i          (tx_detrx_req_i),
  .tx_ack_i                (tx_ack_i),
  .tx_detrx_result_i       (tx_detrx_result_i),
  // PMA SUP interface
  .mplla_en_i              (mplla_en_i),
  .mpllb_en_i              (mpllb_en_i),
  .mplla_state_i           (mplla_state_i),
  .mpllb_state_i           (mpllb_state_i),
  // PMA MPLLA clocks
  .mplla_word_clk_i        (mplla_word_clk_i),
  .mplla_dword_clk_i       (mplla_dword_clk_i),
  .mplla_qword_clk_i       (mplla_qword_clk_i),
  .mplla_oword_clk_i       (mplla_oword_clk_i),
  .mplla_div66_clk_i       (mplla_div66_clk_i),
  .mplla_div33_clk_i       (mplla_div33_clk_i),
  .mplla_div16p5_clk_i     (mplla_div16p5_clk_i),
  .mplla_div_clk_i         (mplla_div_clk_i),
  // PMA MPLLB clocks
  .mpllb_word_clk_i        (mpllb_word_clk_i),
  .mpllb_dword_clk_i       (mpllb_dword_clk_i),
  .mpllb_qword_clk_i       (mpllb_qword_clk_i),
  .mpllb_oword_clk_i       (mpllb_oword_clk_i),
  .mpllb_div_clk_i         (mpllb_div_clk_i),
  // PMA RX clock
  .rx_clk_i                (rx_clk_i),
  // PMA TX interface
  .tx_pma_clk_i            (tx_pma_clk_i),
  .tx_pma_reset_i          (tx_pma_reset_i),
  .tx_pma_req_i            (tx_pma_req_i),
  .tx_pma_pstate_i         (tx_pma_pstate_i),
  .tx_pma_lpd_i            (tx_pma_lpd_i),
  .tx_pma_width_i          (tx_pma_width_i),
  .tx_pma_rate_i           (tx_pma_rate_i),
  .tx_pma_mpllb_sel_i      (tx_pma_mpllb_sel_i),
  .tx_pma_detrx_req_i      (tx_pma_detrx_req_i),
  .tx_pma_ack_i            (tx_pma_ack_i),
  .tx_pma_detrx_result_i   (tx_pma_detrx_result_i),
  // Internal from/to other Raw PCS lanes (pcs_raw_lane)
  .lane_mplla_en_in_i      (lane_mplla_en_in_i),
  .lane_mpllb_en_in_i      (lane_mpllb_en_in_i),
  .lane_mplla_en_out_i     (lane_mplla_en_out_i),
  .lane_mpllb_en_out_i     (lane_mpllb_en_out_i),
  // CREG interface
  .cr_rd_data              (cr_tx_ctl_rd_data),
  .cr_wr_data              (cr_wr_data),
  .cr_wr_en                (cr_wr_en),
  .cr_sel                  (cr_tx_ctl_sel),
  // Scan interface
  .scan_mode_i             (scan_mode_i),
  .scan_shift_cg_i         (scan_shift_cg_i),
  .scan_set_rst_i          (scan_set_rst_i)
);

// %%CREG_BLOCK RX_CTL - pcs_raw_rx_ctl(0xE0)
//
dwc_e12mp_phy_x4_ns_pcs_raw_rx_ctl rx_ctl (
  // Clocks and resets
  .cr_clk                   (cr_clk),
  .cr_rst                   (cr_lane_rst),
  .ref_range                (ref_range),
  // PCS RX interface
  .rx_reset_i               (rx_reset_i),
  .rx_req_i                 (rx_req_i),
  .rx_rate_i                (rx_rate_i),
  .rx_width_i               (rx_width_i),
  .rx_pstate_i              (rx_pstate_i),
  .rx_lpd_i                 (rx_lpd_i),
  .rx_ref_ld_val_i          (rx_ref_ld_val_i),
  .rx_vco_ld_val_i          (rx_vco_ld_val_i),
  .rx_cdr_vco_lowfreq_i     (rx_cdr_vco_lowfreq_i),
  .rx_adapt_afe_en_i        (rx_adapt_afe_en_i),
  .rx_adapt_dfe_en_i        (rx_adapt_dfe_en_i),
  .rx_eq_att_lvl_i          (rx_eq_att_lvl_i),
  .rx_eq_vga1_gain_i        (rx_eq_vga1_gain_i),
  .rx_eq_vga2_gain_i        (rx_eq_vga2_gain_i),
  .rx_eq_ctle_pole_i        (rx_eq_ctle_pole_i),
  .rx_eq_ctle_boost_i       (rx_eq_ctle_boost_i),
  .rx_eq_dfe_tap1_i         (rx_eq_dfe_tap1_i),
  .rx_disable_i             (rx_disable_i),
  .rx_data_en_i             (rx_data_en_i),
  .rx_cdr_track_en_i        (rx_cdr_track_en_i),
  .rx_offcan_cont_i         (rx_offcan_cont_i),
  .rx_adapt_cont_i          (rx_adapt_cont_i),
  .rx_ack_i                 (rx_ack_i),
  .rx_los_i                 (rx_los_i),
  .rx_valid_i               (rx_valid_i),
`ifdef DWC_E12MP_X4NS_RX_CDR_PPM_DETECTOR_ADDED
  .rx_cdr_ppm_max_i         (rx_cdr_ppm_max_i),
`endif
  // Initial power-up done status (from aon_lane register)
  .lane_init_pwrup_done_r   (lane_init_pwrup_done_r),
`ifdef DWC_E12MP_X4NS_RX_CDR_PPM_DETECTOR_ADDED
  .rx_cdr_detector_en_r           (rx_cdr_detector_en_r),
  .rx_cdr_ppm_monitor_mode_r      (rx_cdr_ppm_monitor_mode_r),
  .rx_cdr_recovery_time_r         (rx_cdr_recovery_time_r),
  .rx_cdr_detector_dis_in_adapt_r (rx_cdr_detector_dis_in_adapt_r),
  .rx_adapt_req_sync              (rx_adapt_req_sync),
`endif
  // RX Adaptation Status and Values (from aon_lane registers)
  .rx_att_adpt_val_r        (rx_att_adpt_val_r),
  .rx_vga_adpt_val_r        (rx_vga_adpt_val_r),
  .rx_ctle_pole_adpt_val_r  (rx_ctle_pole_adpt_val_r),
  .rx_ctle_boost_adpt_val_r (rx_ctle_boost_adpt_val_r),
  .rx_dfe_tap1_adpt_val_r   (rx_dfe_tap1_adpt_val_r),
  .rx_dfe_tap2_adpt_val_r   (rx_dfe_tap2_adpt_val_r),
  .rx_dfe_tap3_adpt_val_r   (rx_dfe_tap3_adpt_val_r),
  .rx_dfe_tap4_adpt_val_r   (rx_dfe_tap4_adpt_val_r),
  .rx_dfe_tap5_adpt_val_r   (rx_dfe_tap5_adpt_val_r),
  .rx_adpt_done_r           (rx_adpt_done_r),
  `ifdef DWC_E12MP_X4NS_RX_VCO_CAL_TOO_COARSE
  .rx_fast_vco_cal_r        (rx_fast_vco_cal_r),
  `endif
  .rx_fast_pwrup_r          (rx_fast_pwrup_r),
  // PMA RX interface
  .rx_pma_reset_i           (rx_pma_reset_i),
  .rx_pma_req_i             (rx_pma_req_i),
  .rx_pma_rate_i            (rx_pma_rate_i),
  .rx_pma_width_i           (rx_pma_width_i),
  .rx_pma_pstate_i          (rx_pma_pstate_i),
  .rx_pma_lpd_i             (rx_pma_lpd_i),
  .rx_pma_ref_ld_val_i      (rx_pma_ref_ld_val_i),
  .rx_pma_vco_ld_val_i      (rx_pma_vco_ld_val_i),
  .rx_pma_cdr_vco_lowfreq_i (rx_pma_cdr_vco_lowfreq_i),
  .rx_pma_adapt_afe_en_i    (rx_pma_adapt_afe_en_i),
  .rx_pma_adapt_dfe_en_i    (rx_pma_adapt_dfe_en_i),
  .rx_pma_eq_att_lvl_i      (rx_pma_eq_att_lvl_i),
  .rx_pma_eq_vga1_gain_i    (rx_pma_eq_vga1_gain_i),
  .rx_pma_eq_vga2_gain_i    (rx_pma_eq_vga2_gain_i),
  .rx_pma_eq_ctle_pole_i    (rx_pma_eq_ctle_pole_i),
  .rx_pma_eq_ctle_boost_i   (rx_pma_eq_ctle_boost_i),
  .rx_pma_eq_dfe_tap1_i     (rx_pma_eq_dfe_tap1_i),
  .rx_pma_eq_dfe_tap2_i     (rx_pma_eq_dfe_tap2_i),
  .rx_pma_eq_dfe_tap3_i     (rx_pma_eq_dfe_tap3_i),
  .rx_pma_eq_dfe_tap4_i     (rx_pma_eq_dfe_tap4_i),
  .rx_pma_eq_dfe_tap5_i     (rx_pma_eq_dfe_tap5_i),
  .rx_pma_data_en_i         (rx_pma_data_en_i),
  .rx_pma_cdr_track_en_i    (rx_pma_cdr_track_en_i),
  .rx_pma_ack_i             (rx_pma_ack_i),
  .rx_pma_los_i             (rx_pma_los_i),
  .rx_pma_valid_i           (rx_pma_valid_i),
`ifdef DWC_E12MP_X4NS_RX_CDR_PPM_DETECTOR_ADDED
  .rx_ppm_drift_vld_i       (rx_ppm_drift_vld),
  .rx_ppm_drift_i           (rx_ppm_drift),
`endif
`ifdef DWC_E12MP_X4NS_RX_CDR_PPM_DETECTOR_ADDED
  // PMA RX clock
  .rx_clk_i                 (rx_clk_i),
`else
  `ifdef DWC_E12MP_X4NS_RX_VCO_CAL_TOO_COARSE
  // PMA RX clock
  .rx_clk_i                 (rx_clk_i),
  `endif
`endif
  // CREG interface
  .cr_rd_data               (cr_rx_ctl_rd_data),
  .cr_wr_data               (cr_wr_data),
  .cr_wr_en                 (cr_wr_en),
  .cr_sel                   (cr_rx_ctl_sel),
  // Scan interface
  .scan_mode_i              (scan_mode_i),
  .scan_set_rst_i           (scan_set_rst_i)
);


// Control register select generation
//
dwc_e12mp_phy_x4_ns_pcs_raw_lane_creg lane_creg (
  .cr_lane_pcs_xface_sel (cr_lane_pcs_xface_sel),
  .cr_lane_fsm_sel       (cr_lane_fsm_sel),
  .cr_lane_aon_sel       (cr_lane_aon_sel),
  .cr_lane_aon_sel2      (cr_lane_aon_sel2),
  .cr_irq_ctl_sel        (cr_irq_ctl_sel),
  .cr_lane_pma_xface_sel (cr_lane_pma_xface_sel),
  .cr_tx_ctl_sel         (cr_tx_ctl_sel),
  .cr_rx_ctl_sel         (cr_rx_ctl_sel),

  .cr_chan_addr          (cr_chan_addr),
  .cr_clk                (cr_clk),
  .cr_rst                (cr_lane_rst),
  .cr_addr               (cr_addr)
);

// Muxed register read
//     
assign cr_rd_data = cr_lane_pcs_xface_rd_data |
                    cr_lane_fsm_rd_data       |
                    cr_irq_ctl_rd_data        |
                    cr_lane_pma_xface_rd_data |
                    cr_tx_ctl_rd_data         |
                    cr_rx_ctl_rd_data         |
                    cr_lane_aon_rd_data;

endmodule
